The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through an underlying channel between the source and drain regions.
After the various MOS transistors have been fabricated, they may be interconnected to form the desired electrical circuits. This interconnections occurs in a series of wafer processing steps collectively referred to as back-end-of-line (BEOL) processing. BEOL processing involves creating metal interconnect wires, formed of copper, for example, that are isolated by dielectric layers, such as silicon dioxide or other low-k insulator material. The various metal layers are interconnected by etching holes (called “vias”) in the insulating material and then depositing another metal material, such as aluminum, within the vias. After the formation of the interconnect wires and vias, one or more dielectric passivation layers may be formed over the integrated circuit. Passivation layers are provided to protect the interconnections from external environmental conditions and to help control the electrical properties of the outer semiconductors layers (such as the outer interconnection layers).
FIG. 1 illustrates a particular problem that has been encountered in the prior art when depositing passivation layers over aluminum-filled vias. As shown in FIG. 1, which illustrates a portion 100 of an integrated circuit structure, an outer copper interconnect wire 110 is formed within a first dielectric layer 102 formed of, for example, silicon dioxide. Second dielectric layer 104 formed of, for example, silicon nitride, and a third dielectric layer 106 formed of, for example, silicon dioxide, are provided overlying the first dielectric layer 102. A via 130 (the vertical and lateral dimensions of which are shown by intersecting arrows) is formed within or through the second and third dielectric layers 104, 106, and over the interconnect wire 110. An aluminum layer 120 is deposited to fill the via 130. As aluminum is typically deposited by conformal means, a gap or void 135 forms in the aluminum layer 120 directly over the via 130, due to the difference in elevation of the bottom of the via 130 (i.e., top of the interconnect wire 110) and the top of the third dielectric layer 106.
When passivation of the aluminum layer 120 is thereafter attempted (using a first passivation layer 122 formed of, for example, silicon dioxide and a second passivation 124 layer overlying the first passivation layer 122 formed of, for example, silicon nitride), relatively poor passivation (i.e., inadequate passivation layer thickness) of the aluminum layer 120 within the gap or void 135 along sidewall edges 150 thereof has been observed, due to the relatively steep angle of incline of such sidewall edges 150. This phenomenon results from a progressively narrowing opening 140 at the top of the gap or void 135 as the passivation layers 122, 124 are deposited. Such poor passivation can lead to device failures as a result of possible exposure to the aforementioned environmental conditions, as well as due to loss of control of the electrical properties of the outer semiconductor layers (such as aluminum layer 120).
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that achieve improved resistance to environmental harms, as well as better control of electrical properties. In this regard, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that avoid the problem of inadequate passivation of aluminum layers formed over vias. Additionally, it is desirable to provide methods for the fabrication of such integrated circuits that are easily integrated into existing process flow schemes used in semiconductor fabrication facilities. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.